1. Field of the Invention
This invention relates to package structures and method of fabricating the same, and, more particularly, to a package structure having a semiconductor component embedded therein and a method of fabricating the same.
2. Description of Related Art
With the rapid development of semiconductor package technology, modern semiconductor devices may have various package types. In a semiconductor device, a chip is installed on and electrically connected to a packaging substrate, and is encapsulated with an encapsulant. In order to reduce the height of the package, the chip may be embedded in the packaging substrate. Such a package not only has a reduced size, but also can improve the electrical functionality thereof.
Referring to FIGS. 1A to 1E, which are cross-sectional views illustrating a method of fabricating a package structure having a semiconductor component embedded therein according to the prior art.
As shown in FIG. 1A, a core board 10 is provided with an opening 100 that penetrates the core board 10. Interlayer circuits 101 are formed on top and bottom sides of the core board 10. Conductive through holes 102 are formed in and penetrate the core board 10. The conductive through holes 102 electrically connect the interlayer circuits 101.
As shown in FIG. 1B, a carrier board 14 having a dielectric material 120a is disposed on a bottom side of the core board 10, and a semiconductor chip 11 having a plurality of electrode pads 100 is received in the opening 100 and is disposed on the dielectric material 120a by an adhesive layer 11a. 
As shown in FIG. 1C, another dielectric material 120b is compressed on a top side of the core board 10 and the semiconductor chip 11, such that the two dielectric materials 120a and 120b form the dielectric layer 12. The dielectric layer 12 is filled in an interval between an opening wall of the opening 100 and the semiconductor chip 11, in order to fix the semiconductor chip 11 in the opening 100. Then, the carrier board 14 is removed.
As shown in FIG. 1D, circuit layers 13 are formed on top and bottom sides of the dielectric layer 12. The circuit layers 13 have conductive vias 130 that are formed in the dielectric layer 12 for electrically connecting to the electrode pads 110 to the interlayer circuits 101. Conductive pads 130a are formed on the top one of the circuit layers 13, and ball-implanting pads 130b are formed on the bottom one of the circuit layers 13.
As shown in FIG. 1E, solder mask layers 15 are formed on the dielectric layer 12 and the circuit layers 13. Cavities 150 are formed in the solder mask layers 15 for exposing the conductive pads 130a and the ball-implanting pads 130b. 
In the prior art, the dielectric layer 12 on two sides of the core board 10 have to be compressed towards the semiconductor chip 12 received in the opening 100 of the core board 10, whereby the semiconductor chip 12 is easily displaced. As shown in FIG. 1C, the left and right intervals between the semiconductor chip 11 and the opening wall of the opening 100 are denoted by t and s, respectively, wherein t<s, and the semiconductor chip 11 has a shaping offset approximately equal to +/−100 μm. In other words, it is hard to locate the semiconductor chip 11 in the opening 100 precisely as desired. As the semiconductor chip 11 is displaced, the electrode pads 110 of the semiconductor chip 11 may not be electrically connected to the conductive vias 130 exactly, as shown in FIG. 1D. Therefore, the package structure may suffer from poor electrical connection quality and low product yield.
Moreover, no heat-dissipating structure is embedded in the opening 100 of the core board 10, so the heat generated by the semiconductor chip 11 embedded in the opening 100 of the core board 10, is inefficiently dissipated. As a result, the semiconductor chip 11 may likely malfunction.
Moreover, the semiconductor chip 11 has to be embedded in the core board 10, which is thicker than the semiconductor chip 11. Accordingly, the thickness of the overall structure is increased significantly due to the core board 10, whereby making the final product fail to meet the low-profile and compact-size requirements for electronic components.
No circuit may be formed on two sides of the core board 10, unless conductive through holes 102 are formed to electrically connect the interlayer circuits 101 and the circuit layers 13 on two sides of the core board 10. Such a package structure is difficult to be fabricated, and has a high cost for fabrication.
Therefore, how to overcome the drawbacks of the prior art is becoming one of the most critical issues in the art.